Models of Testable Timed Moore Finite State Machines

Abstract

The work proposes a method of designing testable digital devices in real time, presented in the form of finite state machines and described using hardware description languages (HDL).

Relevance. The relevance of the work lies in the possibility of diagnosing digital devices in real time during active operation.

Research methods. The main research method is the introduction of hardware redundancy in the form of an additional HDL code blocks in the device description code and additional fragments on the temporal state diagram. The proposed approach provides a way to set timed FSM into an arbitrary state without synchronizing sequences and internal timer modification within a fixed number of clock cycles. This increases the testability and observability of the digital device allowing to automate the process of diagnostic experiments creation.

Conclusions. The problem of testable real-time devices based on easy-to-test Moore FSM design has been solved. The proposed method allows to set the automata into an arbitrary state within a fixed time. This approach makes it possible to significantly simplify the process of device diagnostics.

Traffic light controller model was used to illustrate the proposed methods. The initial model was extended with an additional input that allows setting the automata into an arbitrary state. Simulation results confirmed the efficiency of the approach. The synthesis results in CAD XILINX ISE showed that hardware costs are less then 20% when the model is extended with an additional debug input for both FPGA and CPLD boards.

The scientific novelty of this paper lies in developing approaches and methods of creating testable HDL models of timed FSM and their combination by modifying the design HDL description. Such methods can be integrated into CAD systems which allows to decrease the overall time of design and verification.

The practical significance of the work is to introduces the HDL pattern of easy-tested timed Moore FSM by introducing additional if-else statements. The propose methodology can be integrated with other verification and testing technics such as assertion based verification, formal methods, and Universal Verification Methodology increasing the overall design reliability.