Investigation of Temperature and Channel Dimension Effects on CMOS Circuit Performance

  • Zitouni Messai ETA Laboratory, Department of electronics, Faculty of technology, University Mohamed El Bachir El Ibrahimi of Bordj Bou Arréridj, Algeria https://orcid.org/0000-0002-2508-3696
  • Abdelhalim Brahimi ETA Laboratory, Department of electronics, Faculty of technology, University Mohamed El Bachir El Ibrahimi of Bordj Bou Arréridj, Algeria; LIS Laboratory, Department of electronics, Faculty of technology, University Ferhat Abbas Sétif 1, Sétif, Algeria
  • Okba Saidani ETA Laboratory, Department of electronics, Faculty of technology, University Mohamed El Bachir El Ibrahimi of Bordj Bou Arréridj, Algeria https://orcid.org/0000-0003-0507-5581
  • Nacerdine Bourouba LIS Laboratory, Department of electronics, Faculty of technology, University Ferhat Abbas Sétif 1, Sétif, Algeria
  • Abderrahim Yousfi ETA Laboratory, Department of electronics, Faculty of technology, University Mohamed El Bachir El Ibrahimi of Bordj Bou Arréridj, Algeria https://orcid.org/0000-0003-2071-728X
DOI: https://doi.org/10.26565/2312-4334-2024-1-44
Keywords: CMOS, Channels dimensions, Temperature, PSPICE

Abstract

This paper presents the impact of temperature variations and alterations in transistor channel dimensions on CMOS (Complementary Metal-Oxide-Semiconductor) circuit technology. To facilitate this investigation, we first identified critical parameters characterizing the device's performance, which could exhibit susceptibility to these influences. The analysis encompassed critical metrics such as the transfer characteristic, drain current, logic levels, inflection points, and truncation points. These parameters enabled us to validate the results obtained from the PSPICE simulator, which demonstrated unequivocal effectiveness. Notably, our simulation results unveiled significant effects resulting from a wide temperature range spanning from -100°C to 270°C, offering valuable in-sights into thermal-induced failures. Additionally, the influence of channel dimension changes on factors like drain current and transfer characteristics, as well as temporal parameters including signal propagation delay and rise and fall times, were meticulously examined and appreciated.

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Published
2024-03-05
Cited
How to Cite
Messai, Z., Brahimi, A., Saidani, O., Bourouba, N., & Yousfi, A. (2024). Investigation of Temperature and Channel Dimension Effects on CMOS Circuit Performance. East European Journal of Physics, (1), 417-425. https://doi.org/10.26565/2312-4334-2024-1-44
Issue
No. 1 (2024): East European Journal of Physics
Section
Original Papers

Copyright (c) 2024 Zitouni Messai, Abdelhalim Brahimi, Okba Saidani, Nacerdine Bourouba, Abderrahim Yousfi

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