Electrothermal Modeling of Self-Heating in Si/GaAs p–n Heterojunctions

Abstract

This work presents a comprehensive electro-thermal analysis of Si/GaAs heterojunctions, focusing on the coupled effects of self-heating, thermal transport, and junction behavior under varying power and temperature conditions. The developed model reveals strong localization of heat near the heterointerface, where Joule heating (10⁶–10⁸ W·m⁻³) generates significant temperature rises of ΔT ≈ 50–150 K and steep gradients up to 10⁵–10⁶ K·m⁻¹. A transition from weak to highly nonlinear electro-thermal behavior is observed as device temperature increases from ~340 K to ~400 K, with hotspot formation at x ≈ 4 μm. The p-Si/n-GaAs configuration reduces peak temperature by 20–30%, indicating improved thermal performance.  Thermal conductivity analysis shows that silicon maintains 3–5× higher conductivity than GaAs over 50–600 K, confirming a strong material mismatch that limits heat dissipation in the GaAs region. Additionally, the built-in potential exhibits pronounced dependence on temperature and doping, decreasing from ~0.5–0.9 eV at low temperature (50–150 K) to ~0.1–0.3 eV at 300 K, and collapsing near 0 eV at ~500 K due to intrinsic carrier effects, while increasing doping (10¹⁴–10¹⁸ cm⁻³) enhances the barrier logarithmically by ~5–6×.  The model demonstrates high accuracy (RMSE ≈ 1.5–3.2 K, MAPE < 2.5%, R² ≈ 0.99), validating its predictive capability. Overall, the results highlight that electro-thermal coupling, thermal conductivity mismatch, and temperature-driven barrier degradation critically impact device performance. These findings provide important guidelines for optimizing thermal management, interface design, and doping strategies to ensure reliable operation of Si/GaAs heterostructures in high-power and high-temperature applications.